I am a Technical Lead and Member of Technical Staff at AMD Research where I lead research on application-driven design of accelerators and future architectures. More generally, my research interests include processor architectures, memory subsystems and security with a specific interest in near-memory accelerators.
I received my M.S. (2013) and Ph.D. (2017) from the University of Michigan, Ann Arbor where I worked on several exciting topics including in-place computing in processor caches, building secure architectures at low cost, realizing intuitive memory models efficiently and improving performance of multi-core runtimes.
My work has been published at several top-tier computer architecture venues (ISCA, MICRO, HPCA) and also at high-performance computing venues (SC). My research has won several awards at and across institutional level and I was an invited participant in Rising Stars in EECS, 2017 workshop. I am also a (co-)inventor on over twelve granted and pending US patent applications.